`timescale 1ns / 1ps

module int_mul (
        input logic clk,
        input logic rst_n,
        input logic calc_en,
        input logic signed[15:0] a,
        input logic signed[15:0] b,
        output logic signed[15:0] c,
        output logic done
    );
        always_ff @(posedge clk or negedge rst_n) begin
            if (!rst_n) begin
                c <= '0;
                done <= 1'b0;
            end else if (calc_en) begin
                c <= a * b;
                done <= 1'b1;
            end else begin
                done <= 1'b0;
            end
        end
endmodule

module int33_addition(
	  input  logic clk,
    input  logic rst_n,
    input  logic calc_en,
    input  logic signed [15:0] a,
    input  logic signed [15:0] b,
    output logic signed [15:0] c,
    output logic done
  );
 	logic signed [15:0] sum_temp;
 	always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      sum_temp <= '0;
      done <= 0;
    end else begin
      if (calc_en) begin
        sum_temp <= a + b;   
        done <= 1'b1;
      end else begin
        done <= 1'b0;
      end
    end	
	end
  assign c = sum_temp;
endmodule